1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on a polysilicon layer.
2. Description of the Related Art
In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as semiconductor device is highly integrated, the line widths of a gate electrode and other patterns become fine. Recently, the line width is reduced below 0.15 .mu.m. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysilicon layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a titanium polycide structure in which a titanium silicide layer is formed on the polysilicon layer, is mainly applied to a semiconductor device over 1GDRAM.
FIG. 1A to FIG. 1E are cross sectional views describing a method of forming a gate electrode with a titanium polycide structure according to a prior art.
Referring to FIG. 1A, a gate insulating layer 12 is formed on a semiconductor substrate 11 by thermal growth or deposition method and a doped polysilicon layer 13 is formed thereon. Next, a titanium silicide(TiSi.sub.x) layer 14 of an amorphous phase is deposited on the polysilicon layer 13 by physical vapor deposition(PVD) using TiSi.sub.x target, as shown in FIG. 1B. Rapid thermal processing(RTP) is then performed at a selected temperature for several seconds, to transform the TiSi.sub.x layer 14 of the amorphous phase into a TiSi.sub.2 layer 14a of a crystalline phase, as shown in FIG. 1C.
Referring to FIG. 1D, a mask insulating layer 15 is formed in the shape of a gate electrode on the TiSi.sub.2 layer 14a, for a conventional self-aligned contact(SAC) process which will be performed after. Here, the mask insulating layer 15 is formed of an oxide layer or a nitride layer. Thereafter, the TiSi.sub.2 layer 14a and the polysilicon layer 13 are etched using the mask insulating layer 15 as an etch mask, to form a gate electrode 100.
Referring to FIG. 1E, for removing damage due to the etching process and recovering the reliability of the gate insulating layer 12, the structure of FIG. 1D is oxidized by re-oxidation process to form an oxide layer 16 on the side wall of the gate electrode 100 and on the surface of the substrate 11. The re-oxidation process is generally performed at the temperature 800.degree. C. or more.
However, when performing the re-oxidation process, the side wall of the TiSi.sub.2 layer 14a of the gate electrode 100 is excessively oxidized due to the fast oxidation rate of the TiSi.sub.2 layer 14a, thereby reducing the line width of the TiSi.sub.2 layer 14a and aggravating the morphology of the gate electrode 100, as shown in FIG. 1E. Therefore, it is difficult to perform ion-implantation for forming a source and a drain subsequently. Furthermore, the resistivity of the gate electrode increases, thereby deteriorating the reliability of a device.